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16-bit, 2 msps, precision sar, differential adc data sheet ad4001 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2017 analog devices, inc. all rights reserved. technical support www.analog.com features throughput: 2 msps maximum inl: 0.4 lsb maximum guaranteed 16-bit no missing codes low power 9.5 mw at 2 msps (vdd only) 80 w at 10 ksps 16 mw at 2 msps (total) snr 96.2 db typical at 1 khz 95.5 db typical at 100 khz thd ?123 db typical at 1 khz ?99 db typical at 100 khz ease of use features reduce system power and complexity input overvoltage clamp circuit reduced nonlinear input charge kickback high-z mode long acquisition phase input span compression fast conversion time allows low spi clock rates spi-programmable modes, read/write capability, status word differential analog input range: v ref 0 v to v ref with v ref between 2.4 v to 5.1 v single 1.8 v supply operation with 1.71 v to 5.5 v logic interface sar architecture: no latency/pipeline delay guaranteed operation: ?40c to 125c serial interface spi-/qspi-/microwire-/dsp-compatible ability to daisy-chain multiple adcs and busy indicator 10-lead, 3 mm 3 mm lfcsp and 10-lead, 3 mm 4.90 mm msop applications automatic test equipment machine automation medical equipment battery-powered equipment precision data acquisition systems general description the ad4001 is a low noise, low power, high speed, 16-bit, 2 msps, precision successive approximation register (sar) analog-to- digital converter (adc). it incorporates ease of use features that lower the signal chain power, reduce signal chain complexity, and enable higher channel density. the high-z mode, coupled with a long acquisition phase, eliminates the need for a dedicated high power, high speed adc driver, thus broadening the range of low power precision amplifiers that can drive this adc directly, while still achieving optimum performance. the input span compression feature enables the adc driver amplifier and the adc to operate off common supply rails without the need for a negative supply while preserving the full adc code range. the low serial peripheral interface (spi) clock rate requirement reduces the digital input/output power consumption, broadens processor options, and simplifies the task of sending data across digital isolation. operating from a 1.8 v supply, the ad4001 has a v ref fully differential input range with v ref ranging from 2.4 v to 5.1 v. the ad4001 consumes only 16 mw at 2 msps with a minimum sck rate of 70 mhz in turbo mode and achieves 0.4 lsb integral nonlinearity error (inl) maximum, guaranteed no missing codes at 16 bits with 96.2 db typical signal-to-noise ratio (snr). the reference voltage is applied externally and can be set independently of the supply voltage. the spi-compatible, versatile serial interface features seven different modes including the ability, using the sdi input, to daisy-chain several adcs on a single 3-wire bus and provides an optional busy indicator. the ad4001 is compatible with 1.8 v, 2.5 v, 3 v, and 5 v logic, using the separate vio supply. the ad4001 is available in a 10-lead msop or a 10-lead lfcsp with operation specified from ?40c to +125c. the device is pin compatible with the ad4003 18-bit, 2 msps, precision sar differential adc. functional block diagram gnd in+ in? sdi sck sdo cnv ad4001 16-bit sar adc serial interface vio ref vdd v ref 0 v ref 0 v ref /2 v ref /2 high-z mode clamp span compression turbo mode status bits 2.5v to 5 v 1.8v 10f 1.8v to 5v 3-wire or 4-wire spi interface (daisy chain, cs) 15368-001 figure 1.
ad4001* product page quick links last content update: 02/23/2017 comparable parts view a parametric search of comparable parts. evaluation kits ? evaluation board for ad4000 series 16/18-bit precision sar adcs documentation data sheet ? ad4001: 16-bit, 2 msps, precision sar, differential adc data sheet user guides ? ug-1042: evaluation board for the ad4000 series 16-/18- bit precision sar adcs software and systems requirements ? ad4000 series fpga device driver tools and simulations ? ad4000 series ibis models reference designs ? cn0385 design resources ? ad4001 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad4001 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
ad4001 data sheet rev. 0 | page 2 of 33 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 7 thermal resistance ...................................................................... 7 esd caution .................................................................................. 7 pin configurations and function descriptions ........................... 8 typical performance characteristics ............................................. 9 terminology .................................................................................... 13 theory of operation ...................................................................... 14 circuit information .................................................................... 14 converte r operation .................................................................. 14 transfer functions ...................................................................... 15 applications information .............................................................. 16 typical application diagrams .................................................. 16 analog inputs .............................................................................. 17 driver amplifier choice ........................................................... 19 ease of drive features ............................................................... 19 voltage reference input ............................................................ 21 powe r supply ............................................................................... 21 digital interface .......................................................................... 21 register read/write functionality ........................................... 22 status word ................................................................................. 24 cs mode, 3 - wire turbo mode ................................................. 25 cs mode, 3 - wire without busy indicator ............................. 26 cs mode, 3 - wire with busy indicator .................................... 27 cs mode, 4 - wire turbo mode ................................................. 28 cs mode, 4 - wire without busy indicator ............................. 29 cs mode, 4 - wire with busy indicator .................................... 30 daisy - chain mode ..................................................................... 31 layout guidelines ....................................................................... 32 evaluating the ad4001 performance ....................................... 32 outline dimensions ....................................................................... 33 ordering guide .......................................................................... 33 revision history 1 / 20 1 7 rev ision 0 : initial version
data sheet ad4001 rev. 0 | page 3 of 33 specifications vdd = 1.71 v to 1.89 v , v io = 1. 71 v to 5 .5 v , v ref = 5 v , all specifications t min to t max , h igh - z m ode disabled, span compression disabled , a nd turbo mode enabled ( f s = 2 msps) , unless otherwise note d. table 1 . parameter test conditions/comments min typ max unit resolution 1 6 bits analog input voltage range v in+ ? v in? ? v ref + v ref v span c ompression enabled ? v ref 0. 8 + v ref 0. 8 v operating input voltage v in+ , v in? to gnd ?0.1 v ref + 0.1 v span c ompression enabled 0.1 v ref 0.9 v ref v common - mode input range v ref /2 ? 0.125 v ref /2 v ref /2 + 0 .125 v common - mode rejection ratio ( cmrr ) f in = 500 khz 6 8 db analog input current acquisition phase , t = 25c 0.3 na high - z mode enabled , converting dc input at 2 msps 1 a throughput complete cycle 500 ns conversion time 2 90 3 20 ns acquisition phase 1 2 90 ns throughput rate 2 0 2 msps transient response 3 250 ns dc accuracy no missing codes 1 6 bits integral nonl inearity error (inl) ? 0. 4 0. 2 + 0 . 4 lsb differential nonl inearity error (dnl) ?0.5 0. 2 +0.5 lsb transition noise 0. 35 lsb zero error ? 1.5 0.1 + 1.5 lsb zero error drift 4 ? 0. 2 8 + 0 .28 ppm/c gain error ? 16.5 0.4 + 1 6 .5 lsb gain error drift 4 ? 0. 23 + 0. 23 ppm/c power supply sensitivity vdd = 1.8 v 5% 0 . 2 5 lsb 1/f noise 5 bandwidth = 0.1 hz to 10 hz 6 v p -p ac accuracy dynamic range 96. 3 db total rms n oise 5 4 v rms f in = 1 khz, ?0.5 dbfs, v ref = 5 v signal -to - noise ratio (snr) 9 5 .6 96. 2 db spurious - free dynamic range (sfdr) 122 db total harmonic distortion (thd) ?123 db signal -to - noise - and - distortion ratio (sinad) 9 5 .5 96 db oversampled dynamic range oversampling ratio (osr) = 256, v ref = 5 v 120 db f in = 1 khz, ?0.5 dbfs, v ref = 2.5 v snr 9 2 .1 93.2 db sfdr 118 db thd ?11 7 db sinad 9 2 9 3 db
ad4001 data sheet rev. 0 | page 4 of 33 parameter test conditions/comments min typ max unit f in = 100 khz, ?0.5 dbfs, v ref = 5 v snr 9 5.5 db thd ? 99 db sinad 93.8 db f in = 400 khz, ?0.5 dbfs, v ref = 5 v snr 91 db thd ?9 2 db sinad 89 db ?3 db input bandwidth 10 mhz aperture delay 1 ns aperture jitter 1 ps rms reference voltage range (v ref ) 2.4 5.1 v current 2 msps, v ref = 5 v 1.1 ma overvoltage clamp i in+ /i in? v ref = 5 v 50 ma v ref = 2.5 v 50 ma v in+ /v in? at maximum i in+ /i in? v ref = 5 v 5.4 v v ref = 2.5 v 3.1 v v in+ /v in? clamp on/off threshold v ref = 5 v 5.25 5.4 v v ref = 2.5 v 2.68 2.8 v deactivation time 360 ns ref current at maximum i in+ /i in? v in+ /v in? > v ref 100 a digital inputs logic levels input low voltage, v il vio > 2.7 v ?0.3 +0.3 vio v vio 2.7 v ?0.3 +0.2 vio v input high voltage, v ih vio > 2.7 v 0.7 vio vio + 0.3 v vio 2.7 v 0.8 vio vio + 0.3 v input low current, i il ?1 +1 a input high current, i ih ?1 +1 a input pin capacitance 6 pf digital outputs data format serial 16 bits, twos complement pipeline delay conversion results available immediately after completed conversion output low voltage, v ol i sink = 500 a 0.4 v output high voltage, v oh i source = ?500 a vio ? 0.3 v power supplies vdd 1.71 1.8 1.89 v vio 1.71 5.5 v standby current vdd = 1.8 v, vio = 1.8 v, t = 25c 1.6 a power dissipation vdd = 1.8 v, vio = 1.8 v, v ref = 5 v 10 ksps, high - z mode disabled 80 w 1 msps, high - z mode disabled 8 mw 2 msps, high - z mode disabled 16 18.5 mw 1 msps, high - z mode enabled 10 mw 2 msps, high - z mode enabled 20 24.5 mw vdd only 2 msps, high - z mode disabled 9.5 mw ref only 2 msps, high - z mode disabled 5.5 mw vio only 2 msps, high - z mode disabled 1.0 mw energy per conversion 8 nj/sample
data sheet ad4001 rev. 0 | page 5 of 33 parameter test conditions/comments min typ max unit temperature range specified performance t min to t max ?40 +125 c 1 the acquisition phase is the time available for the input sampling capacitors to ac quire a new input with the adc running at a throughput rate of 2 msps. 2 a throughput rate of 2 msps can only be achieved with turbo mode enabled and a minimum sck rate of 70 mhz. refer to table 4 fo r the maximum achievable throughput for different modes of operation. 3 transient response is the time required for the adc to acquire a full-scale input step to 1 lsb accuracy. 4 the minimum and maximum values are guaranteed by characterization, not production tested. 5 see the 1/f noise plot in figure 18. timing specifications vdd = 1.71 v to 1.89 v, vio = 1.71 v to 5.5 v, v ref = 5 v, all specifications t min to t max , high-z mode disabled, span compression disabled, and turbo mode enabled (f s = 2 msps), unless otherwise noted. see figure 2 for the timing voltage levels. table 2. digital interface timing parameter symbol min typ max unit conversion timecnv rising edge to data available t conv 290 320 ns acquisition phase 1 t acq 290 ns time between conversions t cyc 500 ns cnv pulse width (cs mode) 2 t cnvh 10 ns sck period (cs mode) 3 t sck vio > 2.7 v 9.8 ns vio > 1.7 v 12.3 ns sck period (daisy-chain mode) 4 t sck vio >2.7 v 20 ns vio > 1.7 v 25 ns sck low time t sckl 3 ns sck high time t sckh 3 ns sck falling edge to data remains valid delay t hsdo 1.5 ns sck falling edge to data valid delay t dsdo vio > 2.7 v 7.5 ns vio > 1.7 v 10.5 ns cnv or sdi low to sdo d15 most significant bit (msb) valid delay (cs mode) t en vio > 2.7 v 10 ns vio > 1.7 v 13 ns cnv rising edge to first sck rising edge delay t quiet1 190 ns last sck falling edge to cnv rising edge delay 5 t quiet2 60 ns cnv or sdi high or last sck falling edge to sdo high impedance (cs mode) t dis 20 ns sdi valid setup time from cnv rising edge t ssdicnv 2 ns sdi valid hold time from cnv rising edge (cs mode) t hsdicnv 2 ns sck valid hold time from cnv rising edge (daisy-chain mode) t hsckcnv 12 ns sdi valid setup time from sck rising edge (daisy-chain mode) t ssdisck 2 ns sdi valid hold time from sck rising edge (daisy-chain mode) t hsdisck 2 ns 1 the acquisition phase is the time available for the input sampling capacitors to ac quire a new input with the adc running at a throughput rate of 2 msps. 2 for turbo mode, t cnvh must match the t quiet1 minimum. 3 a throughput rate of 2 msps can only be achieved with turbo mode enabled and a minimum sck rate of 70 mhz. 4 a 50% duty cycle is assumed for sck. 5 see figure 22 for sinad vs. t quiet2 . x% vio 1 y% vio 1 v ih 2 v il 2 v il 2 v ih 2 t delay t delay 1 for vio 2.7v, x = 80, and y = 20; for vio > 2.7v, x = 70, and y = 30. 2 minimum v ih and maximum v il used. see digital inputs specifications in table 1. 15368-002 figure 2. voltage levels for timing
ad4001 data sheet rev. 0 | page 6 of 33 table 3 . register read/write timing parameter symbol min typ max unit read/write operation cnv pulse width 1 t cnvh 10 ns sck period t sck vio > 2.7 v 9.8 ns vio > 1.7 v 12. 3 ns sck low time t sckl 3 ns sck high time t sckh 3 ns read operation cnv low to sdo d1 5 msb valid delay t en vio > 2.7 v 10 ns vio > 1.7 v 13 ns sck falling edge to data remains valid t hsdo 1.5 ns sck falling edge to data valid delay t dsdo vio > 2.7 v 7.5 ns vio > 1.7 v 1 0.5 ns cnv r ising e dge to sdo high impedance t dis 20 ns write operation sdi valid setup time from sck rising edge t ssdisck 2 ns sdi valid hold time from sck rising edge t hsdisck 2 ns cnv rising edge to sck edge hold time t hcnvsck 0 ns cnv falling edge to sck active edge setup time t scnvsck 6 ns 1 for turbo mode, t cnvh must match the t quiet1 minimum. table 4 . achievable throughput for different modes of operation parameter test conditions/comments min typ max unit throughput , cs mode 3 - wire and 4 - wire turbo mode f sck = 100 mhz, vio 2.7 v 2 msps f sck = 80 mhz, vio < 2.7 v 2 msps 3 - wire and 4 - wire turbo mode and six status bits f sck = 100 mhz, vio 2.7 v 2 msps f sck = 80 mhz, vio < 2.7 v 1. 8 6 msps 3 - wire and 4 - wire mode f sck = 100 mhz, vio 2.7 v 1.82 msps f sck = 80 mhz, vio < 2.7 v 1.69 msps 3 - wire and 4 - wire mode and six status bits f sck = 100 mhz, vio 2.7 v 1.64 msps f sck = 80 mhz, vio < 2.7 v 1.5 msps
data sheet ad4001 rev. 0 | page 7 of 33 absolute maximum rat ings table 5 . parameter rating analog inputs in+, in? to gnd 1 ?0.3 v to v ref + 0. 4 v or 50 ma supply voltage ref , vio to gnd ?0.3 v to +6.0 v vdd to gnd ?0.3 v to + 2.1 v vdd to vio ?6 v to +2.4 v digital inputs to gnd ?0.3 v to vio + 0.3 v digital outputs to gnd ?0.3 v to vio + 0.3 v storage temperature range ?65c to +150c junction temperature 150c lead temperature soldering 260c reflow as per jedec j - std -020 esd ratings human body model 4 kv machine model 200 v field - induced charged device model 1.25 kv 1 see the analog inputs section for an explanation of in+ and in?. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. note t hat the clamp cannot sustain the overvoltage condition for an indefinite time. thermal resistance t hermal performance is directly linked to printed circuit board (pcb) design and operating environment. careful attention to pcb thermal design is required. table 6 . thermal resistance package type ja jc unit rm - 10 1 147 38 c/w cp -10-9 1 114 33 c/w 1 test condition 1: thermal impedance simulated values are based upon use of 2s2p jedec pcb. see the ordering guide . esd caution
ad4001 data sheet rev. 0 | page 8 of 33 pin configurations and function descriptions ref 1 vdd 2 in+ 3 in? 4 gnd 5 vio 10 sdi 9 sck 8 sdo 7 cnv 6 ad4001 top view (not to scale) 15368-003 figure 3. 10-lead ms op pin configuration 1 ref 2 vdd 3 in+ 4 in? 5 gnd 10 vio 9sdi 8sck 7sdo 6cnv ad4001 top view (not to scale) notes 1. connect the exposed pad to gnd. this connection is not required to meet the specified performance. 15368-004 figure 4. 10-lead lfcsp pin configuration table 7. pin function descriptions pin no. mnemonic type 1 description 1 ref ai reference input voltage. the v ref range is 2.4 v to 5.1 v. this pin is referred to the gnd pin and must be decoupled closely to the gnd pin with a 10 f, x7r ceramic capacitor. 2 vdd p 1.8 v power supply. the vdd range is 1.71 v to 1.89 v. bypass vdd to gnd with a 0.1 f ceramic capacitor. 3 in+ ai differential positive analog input. 4 in? ai differential negative analog input. 5 gnd p power supply ground. 6 cnv di convert input. this input has multiple functions. on its leading edge, it initiates the conversions and selects the interface mode of the device: daisy-chain mode or cs mode. in cs mode, the sdo pin is enabled when cnv is low. in daisy-chain mo de, the data is read when cnv is high. 7 sdo do serial data output. the conversion result is output on this pin. it is synchronized to sck. 8 sck di serial data clock input. when the device is select ed, the conversion result is shifted out by this clock. 9 sdi di serial data input. this input provides multiple features. it selects the interface mode of the adc as follows: daisy-chain mode is selected if sdi is low during the cnv rising edge. in this mode, sdi is used as a data input to daisy-chain the conversion results of two or more adcs onto a single sdo line. the digital data level on sdi is output on sdo with a delay of 16 sck cycles. cs mode is selected if sdi is high during the cnv risi ng edge. in this mode, either sdi or cnv can enable the serial output signals when low. if sdi or cnv is low when the conversion is complete, the busy indicator feature is enabled. with cnv low, the device can be programmed by clocking in a 16-bit word on sdi on the rising edge of sck. 10 vio p input/output interface digital power. nominally, this pin is at the same supply as the host interface (1.8 v, 2.5 v, 3 v, or 5 v). bypass vio to gnd with a 0.1 f ceramic capacitor. n/a 2 epad p exposed pad (lfcsp only). connect the exposed pad to gnd. this connection is not required to meet the specified performance. 1 ai is analog input, p is power, di is digital input, and do is digital output. 2 n/a means not applicable.
data sheet ad4001 rev. 0 | page 9 of 33 typical performance characteristics vdd = 1.8 v , vio = 3.3 v , v ref = 5 v , t = 25c, high - z mode disabled, span compression disabled , and turbo mode enabled ( f s = 2 msps ), unless otherwise noted. ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 8192 16384 24576 32768 40960 49152 57344 65536 in l (lsb) code ?4 0 c +2 5 c +12 5 c 15368-200 figure 5. inl vs. code for various temperature s, v ref = 5 v code ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 8192 16384 24576 32768 40960 49152 57344 65536 in l (lsb) ?4 0 c +2 5 c +12 5 c 15368-201 figure 6. inl vs. code for various temperature s, v ref = 2.5 v ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 8192 16384 24576 32768 40960 49152 57344 65536 in l (lsb) code high-z enabled span compression enabled 15368-407 figure 7 . inl vs. code, high - z and span compression modes enabled, v ref = 5 v ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 8192 16384 24576 32768 40960 49152 57344 65536 dn l (lsb) code ?4 0 c +2 5 c +12 5 c 15368-203 figure 8. dnl vs. code for various temperature s, v ref = 5 v code ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 8192 16384 24576 32768 40960 49152 57344 65536 dn l (lsb) ?4 0 c +2 5 c +12 5 c 15368-204 figure 9. dnl vs. code for various temperature s, v ref = 2.5 v ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 8192 16384 24576 32768 40960 49152 57344 65536 dnl (lsb) code high-z enabled span compression enabled 15368-410 figure 10 . dnl vs. code, high - z and span compression modes enabled, v ref = 5 v
ad4001 data sheet rev. 0 | page 10 of 33 15368-205 0 200000 400000 600000 800000 1000000 1200000 32766 32767 32768 32769 32770 code count code v ref = 5v v ref = 2.5v figure 11 . histogram of a dc input at code center, v ref = 2.5 v and v ref = 5 v 0 ?60 ?160 ?120 ?20 ?100 ?80 ?140 ?40 ?180 fundamental amplitude (db) 100 100k 10k 1k 1m frequency (hz) v ref = 5v snr = 96.25db thd = ?124.30db sinad = 96.23db 15368-207 figure 12 . 1 khz, 0.5 dbfs input tone fft, wide view , v ref = 5 v 0 ?60 ?160 ?120 ?20 ?100 ?80 ?140 ?40 ?180 fundamental amplitude (db) 1k 100k 10k 1m frequency (hz) v ref = 5v snr = 95.48db thd = ?98.63db sinad = 93.84db 15368-210 figure 13 . 100 khz, 0.5 dbfs input tone fft, wide view 15368-208 0 100000 200000 300000 400000 500000 600000 32766 32767 32768 32769 32770 code count code v ref = 5v v ref = 2.5v figure 14 . histogram of a dc input at code transition, v ref = 2.5 v and v ref = 5 v 0 ?60 ?160 ?120 ?20 ?100 ?80 ?140 ?40 ?180 fundamental amplitude (db) 100 100k 10k 1k 1m frequency (hz) v ref = 2.5v snr = 93.12db thd = ?118.26db sinad = 93.11db 15368-209 figure 15 . 1 khz, 0.5 dbfs input tone fft, wide view, v ref = 2.5 v 0 ?60 ?160 ?120 ?20 ?100 ?80 ?140 ?40 ?180 fundamental amplitude (db) 1k 100k 10k 1m frequency (hz) v ref = 5v snr = 91.04db thd = ?91.47db sinad = 88.85db 15368-213 figure 16 . 400 khz, 0.5 dbfs input tone fft, wide view
data sheet ad4001 rev. 0 | page 11 of 33 15368-219 92.5 93.0 93.5 94.0 94.5 95.0 95.5 96.0 96.5 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 snr, sinad (db) reference vo lt age (v) enob (bits) enob snr sinad figure 17 . snr, sinad, and enob vs. reference voltage 60 58 55 56 59 57 54 adc output reading (v) 0 9 8 5 6 7 4 3 2 1 10 time (seconds) 15368-217 figure 18 . 1/f noise for 0.1 hz to 10 hz bandwidth, 50 k sps , 2500 samples averaged per reading 15368-212 95 100 105 110 115 120 125 130 0 2 4 8 16 32 64 128 256 512 1024 2048 snr (db) decimation rate dynamic range frequency = 1khz frequency = 10khz figure 19 . snr vs. decimation rate for various input frequencies 15368-216 ?132 ?130 ?128 ?126 ?124 ?122 ?120 ?118 ?116 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 120 121 122 123 124 125 126 127 128 129 reference vo lt age (v) thd (db) sfdr (db) sfdr thd figure 20 . thd and sfdr vs. reference voltage 1.1 0.9 0.6 0.7 1.0 0.8 0.5 0.4 reference current ( ma) 2.4 4.8 4.5 3.9 4.2 3.6 3.3 3.0 2.7 5.1 reference voltage (v) 15368-218 figure 21 . reference current vs. reference voltage 15368-215 89 90 91 92 93 94 95 96 97 0 20 40 60 80 100 sinad (db) t quiet2 (seconds) vio = 1.89v vio = 3.6v vio = 5.5v figure 22 . sinad vs. t quiet2
ad4001 data sheet rev. 0 | page 12 of 33 15.63 15.64 15.65 15.66 15.67 15.68 15.69 15.70 15.71 15.72 15.73 95.9 96.0 96.1 96.2 96.3 96.4 96.5 ?40 ?20 0 20 40 60 80 100 120 temper a ture (c) enob (bits) srn, sinad (db) snr sinad enob 15368-222 figure 23 . snr, sinad, and enob vs. temperature, f in = 1 khz 8 7 3 5 6 4 1 2 0 operating current (ma) vdd high-z disabled vdd high-z enabled ref high-z disabled ref high-z enabled vio high-z disabled vio high-z enabled ?40 100 80 60 40 20 0 ?20 120 temperature (c) 15368-223 figure 24 . operating currents vs. temperature 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 ?40 ?20 0 20 40 60 80 100 120 zero error, gain error (lsb) temper a ture (c) zero error pfs error nfs error 15368-221 figure 25 . zero error and gain error vs. temperature , positive full scale (pfs) and negative full scale (nfs ) 126.3 126.4 126.5 126.6 126.7 126.8 126.9 127.0 127.1 ?129 ?128 ?127 ?126 ?125 ?124 ?123 ?122 ?121 ?120 ?119 ?118 ?40 ?20 0 20 40 60 80 100 120 temper a ture (c) sfdr (db) thd (db) thd sfdr 15368-225 figure 26 . thd and sfdr vs. temperature, f in = 1 khz 25.0 20.0 10.0 15.0 5.0 22.5 17.5 7.5 12.5 2.5 0 standby current ( a) ?40 100 80 60 40 20 0 ?20 120 temperature (c) 15368-226 figure 27 . standby current vs. temperature 23 21 13 17 19 15 9 11 7 5 t dsdo (ns) 0 100 80 60 40 200 180 160 140 20 220 120 load capacitance (pf) vio = 5v vio = 3.3v vio = 1.8v 15368-224 figure 28 . t dsdo vs. load capacitance
data sheet ad4001 rev. 0 | page 13 of 33 terminology integral nonlinearity error (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negati ve full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line (see figure 30). differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it is often specified i n terms of resolution for which no missing codes are guaranteed. zero error zero error is the difference between the ideal midscale voltage, that is, 0 v, from the actual voltage producing the midscale output code, that is, 0 lsb. gain error the first transition (from 100 ... 00 to 100 ... 01) occurs at a level ? lsb above nominal negative full scale (?4.999981 v for the 5 v range). the last transition (from 011 10 to 011 11) occurs for an analog voltage 1? lsb below the nominal full scal e (+4.999943 v for the 5 v range). the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. spurious - free dynamic range (sf dr) sfdr is the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad as follows: eno b = ( sinad db ? 1.76)/6.02 enob is expressed in bits. noise free code resolution noise free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. it is calculated as noise free code resolution = log 2 (2 n / peak - to - peak noise ) noise free code resolution is expressed in bits. effective resolution effective resolution is calculated as effective resolution = log 2 (2 n / rms input noise ) effective resolution is expressed in bits. total harmonic distortion (thd) thd i s the ratio of the rms sum of the first five harmonic components to the rms value of a full - scale input signal and is expressed in decibels. dynamic range dynamic range is the ratio of the rms value of the full scale to the total rms noise measured. the va lue for dynamic range is expressed in decibels. it is measured with a signal at ?60 dbfs so that it includes all noise sources and dnl artifacts. signal -to - noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal -to - noise - and - distortion ratio (sinad) sinad is the ratio of the rms value of the actual input signal to the rms sum of a ll other spectral components that are less than the nyquist frequency, including harmonics but excluding dc. the value of sinad is expressed in decibels. aperture delay aperture delay is the measure of the acquisition performance and is the time between the rising edge of the cnv input and when the input signal is held for a conversion. transient response transient response is the time required for the adc to acquire a full - scale input step to 1 lsb accuracy. common - mode rejection ratio (cmrr) cmrr is th e ratio of the power in the adc output at the frequency, f, to the power of a 200 mv p - p sine wave applied to the common - mode voltage of in+ and in? at the frequency, f. cmrr (db) = 10log( p adc_in / p adc_out ) where: p adc_in is the common - mode power at the fre quency, f, applied to the in+ and in? inputs. p adc_out is the power at the frequency, f, in the adc output. power supply rejection ratio (psrr) psrr is the ratio of the power in the adc output at the frequency, f, to the power of a 200 mv p - p sine wave ap plied to the adc vdd supply at the frequency, f. psrr (db) = 10 log( p vdd_in / p adc_out ) where: p vdd_in is the power at the frequency, f, at the vdd pin. p adc_out is the power at the frequency, f, in the adc output.
ad4001 data sheet rev. 0 | page 14 of 33 theory of operation 15368-007 comp control logic switches control busy output code cnv c c 2c 16,384c 4c 32,768c lsb sw+ msb lsb sw? msb c c 2c 16,384c 4c 32,768c in+ ref gnd in? figure 29. adc simplified schematic circuit information the ad4001 is a high speed, low power, single-supply, precise, 16-bit adc based on a sar architecture. the ad4001 is capable of converting 2,000,000 samples per second (2 msps) and powers down between conversions. when operating at 10 ksps, for example, it typically consumes 80 w, making it ideal for battery-powered applications because its power scales linearly with throughput. the ad4001 has a valid first conversion after being powered down for long periods. the ad4001 provides the user with an on-chip track-and-hold feature and does not exhibit any pipeline delay or latency, making it ideal for multiplexed applications. the ad4001 incorporates a multitude of unique ease of use features that result in a lower system power and footprint. the ad4001 has an internal voltage clamp that protects the device from overvoltage damage on the analog inputs. the analog input incorporates circuitry that reduces the nonlinear charge kickback seen from a typical switched capacitor sar input. this reduction in kickback, combined with a longer acquisition phase, means reduced settling requirements on the driving amplifier. this combination allows the use of lower bandwidth and lower power amplifiers as drivers. it has the additional benefit of allowing a larger resistor value in the input rc filter and a corresponding smaller capacitor, which results in a smaller rc load for the amplifier, improving stability and power dissipation. high-z mode can be enabled via the spi interface by programming a register bit (see table 14). when high-z mode is enabled, the adc input has a low input charging current at low input signal frequencies, as well as improved distortion over a wide frequency range up to 100 khz. for frequencies above 100 khz and multiplexing, disable high-z mode. for single-supply applications, a span compression feature creates additional headroom and footroom for the driving amplifier to access the full range of the adc. the fast conversion time of the ad4001 , along with turbo mode, allows low clock rates to read back conversions even when running at the full 2 msps throughput rate. note that a throughput rate of 2 msps can be achieved only with turbo mode enabled and a minimum 70 mhz sck rate. the ad4001 can interface to any 1.8 v to 5 v digital logic family. it is available in a 10-lead msop or a tiny 10-lead lfcsp that allows space savings and flexible configurations. the ad4001 is pin for pin compatible with some of the 14-/16-/ 18-bit precision sar adcs listed in table 8. table 8. msop and lfcsp 14-/ 16-/18-bit precision sar adcs bits 100 ksps 250 ksps 400 ksps to 500 ksps 1000 ksps 18 1 ad7989-1 2 ad7691 2 ad7690 , 2 ad7989-5 2 ad4003 , ad7982 , 2 ad7984 2 16 1 ad7684 ad7687 ad7688 , 2 ad7693 2 ad4001, ad7915 2 16 3 ad7680 , ad7683 , ad7988-1 2 ad7685, 2 ad7694 ad7686 , 2 ad7988-5 ad4000, ad7980 , 2 ad7983 2 14 3 ad7940 ad7942 2 ad7946 2 not applicable 1 true differential. 2 pin for pin compatible. 3 pseudo differential. converter operation the ad4001 is a sar-based adc using a charge redistribution sampling digital-to-analog converter (dac). figure 29 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 16 binary weighted capacitors that are connected to the comparator inputs. during the acquisition phase, terminals of the array tied to the input of the comparator are connected to gnd via the sw+ and sw? switches. all independent switches connect the other terminal of each capacitor to the analog inputs. therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the in+ and in? inputs.
data sheet ad4001 rev. 0 | page 15 of 33 when the acquisition phase is complete and the cnv input goes high, a conversion phase initiates. when the conversion phase begins, sw+ and sw? are opened first. the two capacitor arrays are then disconnected from the inputs and connected to the gnd input. the differential voltage between the in+ and in? inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between gnd and v ref , the comparator input varies by binary weighted voltage steps (v ref /2, v ref /4, , v ref /65,536). the control logic toggles these switches, starting with the msb, to bring the comparator back into a balanced condition. after the completion of this process, the control logic generates the adc output code and a busy signal indicator. because the ad4001 has an on-board conversion clock, the serial clock, sck, is not required for the conversion process. transfer functions the ideal transfer characteristics for the ad4001 are shown in figure 30 and table 9. 100...000 100...001 100...010 011...101 011...110 011...111 adc code (twos complement) analog input +fsr ? 1.5 lsb +fsr ? 1 lsb ?fsr + 1 lsb ?fsr ?fsr + 0.5 lsb 15368-008 figure 30. adc ideal transfer func tion (fsr is full-scale range) table 9. output codes and ideal input voltages description analog input, v ref = 5 v v ref = 5 v with span compression enabled digital output code (hex) +fsr ? 1 lsb +4.999847 v +3.999878 v 0x7fff 1 midscale + 1 lsb +152.6 v +122.1 v 0x0001 midscale 0 v 0 v 0x0000 midscale ? 1 lsb ?152.6 v ?122.1 v 0xffff ?fsr + 1 lsb ?4.999847 v ?3.999878 v 0x8001 ?fsr ?5 v ?4 v 0x8000 2 1 this output code is also the code for an overranged analog input (v in+ ? v in? above v ref ). 2 this output code is also the code for an underranged analog input (v in+ ? v in? below ?v ref ).
ad4001 data sheet rev. 0 | page 16 of 33 applications information typical application diagrams figure 31 shows an example of the recommended connection diagram for the ad4001 when multiple supplies are available. this configuration is used for best performance because the amplifier supplies can be selected to allow the maximum signal range. figure 32 shows a recommended connection diagram when using a single-supply system. this setup is preferable when only a limited number of rails are available in the system and power dissipation is of critical importance. figure 33 shows a recommended connection diagram when using a fully differential amplifier. c r v+ ref vdd vio gnd in+ in? sdi sck sdo cnv ad4001 3-wire/4-wire interface 1.8v 1.8v to 5v v + +6.5 v digital host (microprocessor/ fpga) v? ?0.5v host supply 0.1f 0.1f 5v c r v? v+ v? amp amp v ref 0v v ref 0v v cm = v ref /2 v cm = v ref /2 ref ldo amp v cm = v ref /2 10f 10k ? 10k ? 15368-009 figure 31. typical application diagram with multiple supplies c r ref vdd vio gnd in+ in? sdi sck sdo cnv ad4001 2 1.8v 1.8v to 5v v +=+5 v digital host (microprocessor/ fpga) host supply 0.1f 0.1f 100nf 100nf 4.096v c r amp amp 0.9 v ref 0.1 v ref 0.9 v ref 0.1 v ref v cm = v ref /2 v cm = v ref /2 ref 1 ldo amp v cm = v ref /2 10f 1 10k ? 10k ? 1 see the voltage reference input section for reference selection. c ref is usually a 10f ceramic capacitor (x7r). 2 span compression mode enabled. 3 see table 10 for rc filter and amplifier selection. 3-wire/4-wire interface 3 15368-010 figure 32. typical application diagram with a single supply
data sheet ad4001 rev. 0 | page 17 of 33 10f ref vdd vio gnd in+ in? sdi sck sdo cnv ad4001 3-wire/4-wire interface 1.8v 1.8v to 5v digital host (microprocessor/ fpga) 4.096v 0.1f v ocm r3 1k ? +in v+ ?in ?out +out r4 1k ? 10k ? 10k? r2 1k ? r r differential amplifier r1 1k ? 0.1f v cm = v ref /2 host supply v? c c ref v + = +5v ldo amp v ref 0 v cm = v ref /2 v ref 0 v cm = v ref /2 0.1f v cm = v ref /2 15368-011 figure 33. typical application diagram with a fully differential amplifier ref vdd vio gnd in+ in? sdi sck sdo cnv ad4001 1.8v to 5v +in ?in r4 1k ? differential amplifier r1 1k ? v? amp +v ref ?v ref 0v 1.8v 10f r3 1k ? v+ ?out +out r2 1k ? r r 0.1f v ref /2 host supply c c ref v + = +5v ldo 10k ? 10k ? v ocm 4.096v 0.1f 0.1f 3-wire/4-wire interface digital host (microprocessor/ fpga) v cm = v ref /2 15368-012 figure 34. typical application diagram for single-ended to differential conversion with a fully differential amplifier analog inputs figure 35 shows an equivalent circuit of the analog input structure, including the overvoltage clamp of the ad4001. input overvoltage clamp circuit most adc analog inputs, in+ and in?, have no overvoltage protection circuitry apart from esd protection diodes. during an overvoltage event, an esd protection diode from an analog input pin (in+ or in?) to ref forward biases and shorts the input pin to ref, potentially overloading the reference or causing damage to the device. the ad4001 internal overvoltage clamp circuit with a larger external resistor (r ext = 200 ) eliminates the need for external protection diodes and protects the adc inputs against dc overvoltages. in applications where the amplifier rails are greater than v ref and less than ground, it is possible for the output to exceed the input voltage range of the device. in this case, the ad4001 internal voltage clamp circuit ensures that the voltage on the input pin does not exceed v ref + 0.4 v and prevents damage to the device by clamping the input voltage in a safe operating range and by avoiding disturbance of the reference, which is particularly important for systems that share the reference among multiple adcs.
ad4001 data sheet rev. 0 | page 18 of 33 if the analog input exceeds the reference voltage by 0.4 v, the internal clamp circuit turns on and the current flows through the clamp into ground, preventing the input from rising further and potentially causing damage to the device. the clamp turns on before d1 (see figure 35) and can sink up to 50 ma of current. when the clamp is active, it sets the ov clamp flag bit in the register that can be read back (see table 14), which is a sticky bit that must be read to be cleared. the status of the clamp can also be checked in the status bits using an overvoltage clamp flag (see table 15). the clamp circuit does not dissipate static power in the off state. note that the clamp cannot sustain the overvoltage condition for an indefinite time. the external rc filter is usually present at the adc input to band limit the input signal. during an overvoltage event, excessive voltage is dropped across r ext , and r ext becomes part of the protection circuit. the r ext value can vary from 200 to 20 k for 15 v protection. the c ext value can be as low as 100 pf for correct operation of the clamp. see table 1 for the input overvoltage clamp specifications. c ext r ext v in ref d1 in+/in? gnd clamp 0v to 15v r in c in d2 c pin 15368-013 figure 35. equivalent analog input circuit differential input considerations the analog input structure allows the sampling of the true differential signal between in+ and in?. by using these differential inputs, signals common to both inputs are rejected. figure 36 shows the common-mode rejection capability of the ad4001 over frequency. it is important to note that the differential input signals must be truly antiphase in nature, 180 out of phase, which is required to keep the common-mode voltage of the input signal within the specified range around v ref /2 shown in table 1. 72 71 70 69 68 67 66 cmrr (db) 100 1k 10k 100k 1m frequency (hz) 15368-303 figure 36. common-mode rejection ra tio vs. frequency, vio = 3.3 v, v ref = 5 v, 25c switched capacitor input during the acquisition phase, the impedance of the analog inputs (in+ or in?) can be modeled as a parallel combination of capacitor c pin and the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 400 and is a lumped component composed of serial resistors and the on resistance of the switches. c in is typically 40 pf and is mainly the adc sampling capacitor. during the conversion phase, where the switches are open, the input impedance is limited to c pin . r in and c in make a single- pole, low-pass filter that reduces undesirable aliasing effects and limits noise. rc filter values the rc filter value and driving amplifier can be selected depending on the input signal bandwidth of interest at the full 2 msps throughput. lower input signal bandwidth means that the rc cutoff can be lower, thereby reducing noise into the converter. for optimum performance at various throughputs, use the recommended rc values (200 , 180 pf) and the ada4807-1 . the rc values in table 10 are chosen for ease of drive considerations and also greater adc input protection. the combination of a large r value (200 ) and small c value result in a reduced dynamic load for the amplifier to drive. the smaller value of c means few stability and phase margin concerns with the amplifier. the large value of r limits the current into the adc input when the amplifier output exceeds the adc input range. table 10. rc filter and amplifier selection for various input bandwidths input signal bandwidth (khz) r () c (pf) recommended amplifier recommended fully differential amplifier <10 see the high-z mode section ada4940-1 <200 200 180 ada4807-1 ada4940-1 >200 200 120 ada4897-1 ada4932-1 multiplexed 200 120 ada4897-1 ada4932-1
data sheet ad4001 rev. 0 | page 19 of 33 driver amplifier choice although the ad4001 is easy to drive, the driver amplifier must meet the following requirements: ? the noise generated by the driver amplifier must be kept low enough to preserve the snr and transition noise performance of the ad4001 . the noise from the driver is filtered by the single-pole, low-pass filter of the ad4001 analog input circuit made by r in and c in , or by the external filter, if one is used. because the typical noise of the ad4001 is 54 v rms, the snr degradation due to the amplifier is ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 2 )( 2 45 54 log20 n db3 loss nef snr where: f ?3 db is the input bandwidth, in megahertz, of the ad4001 (10 mhz) or the cutoff frequency of the input filter, if one is used. n is the noise gain of the amplifier (for example, 1 in buffer configuration). e n is the equivalent input noise voltage of the op amp in nv/hz. ? for ac applications, the driver must have a thd performance commensurate with the ad4001. ? for multichannel multiplexed applications, the driver amplifier and the ad4001 analog input circuit must settle for a full-scale step onto the capacitor array at a 16-bit level (0.0001525%, 15.25 ppm). in the data sheet of the amplifier, settling at 0.1% to 0.01% is more commonly specified. this settling may differ significantly from the settling time at a 16-bit level and must be verified prior to driver selection. single to differential driver for applications using a single-ended analog signal, either bipolar or unipolar, the ada4940-1 single-ended to differential driver allows a differential input to the device. the schematic is shown in figure 34. high frequency input signals the ad4001 ac performance over a wide input frequency range is shown in figure 37. unlike other traditional sar adcs, the ad4001 ac performance holds up to the nyquist frequency. 15368-211 14.0 14.2 14.4 14.6 14.8 15.0 15.2 15.4 15.6 15.8 88 89 90 91 92 93 94 95 96 97 srn, sinad (db) snr sinad enob 1k 10k 100k 1m input frequency (hz) figure 37. snr, sinad, and enob vs. input frequency 1k 10k 100k 1m input frequency (hz) sfdr (db) thd (db) 15368-214 90 95 100 105 110 115 120 125 ?125 ?120 ?115 ?110 ?105 ?100 ?95 ? 90 thd sfdr figure 38. thd and sfdr vs. input frequency ease of drive features input span compression in single-supply applications, it is desirable to use the full range of the adc; however, the amplifier can have some headroom and footroom requirements, which can be a problem, even if it is a rail-to-rail input and output amplifier. the use of span compression increases the headroom and footroom available to the amplifier by reducing the input range by 10% from the top and bottom of the range while still accessing all available adc codes (see figure 39). the snr decreases by approximately 1.9 db (20 log(8/10)) for the reduced input range when span compression is enabled. span compression is disabled by default but can be enabled by writing to the relevant register bit (see the digital interface section). adc v ref = 4.096v digital output all 2 n codes +fsr ?fsr 90% of v ref = 3.69v 10% of v ref = 0.41v a nalog input 5v in+ 15368-300 figure 39. span compression
ad4001 data sheet rev. 0 | page 20 of 33 high-z mode the ad4001 incorporates high-z mode, which reduces the nonlinear charge kickback when the capacitor dac switches back to the input at the start of acquisition. figure 40 shows the input current of the ad4001 with high-z mode enabled and disabled. the low input current makes the adc easier to drive than the traditional sar adcs available in the market, even with high-z mode disabled. the input current reduces further to sub microampere range when high-z mode is enabled. the high-z mode is disabled by default but can be enabled by writing to the register (see table 14). disable high-z mode for input frequencies above 100 khz or multiplexing. 15 6 ?12 ?6 12 0 3 ?9 9 ?3 ?15 input current (a) ?5 3 1 ?1 ?3 5 2 0 ?2 ?4 4 input differential voltage (v) 25c high-z enabled 25c high-z disabled 15368-301 figure 40. input current vs. input differential voltage, vio = 3.3 v, v ref = 5 v system designers looking to achieve the optimum data sheet performance from high resolution precision sar adcs are often forced to use a dedicated high power, high speed amplifier to drive the traditional switched capacitor sar adc inputs for their precision applications, which is one of the common pain points encountered in designing a precision data acquisition signal chain. the benefits of high-z mode are low input current for slow (<10 khz) or dc type signals and improved distortion (thd) performance over a frequency range of up to 100 khz. high-z mode allows a choice of lower power and bandwidth precision amplifiers with a lower rc filter cutoff to drive the adc, removing the need for dedicated high speed adc drivers, which saves system power, size, and cost in precision, low bandwidth applications. high-z mode allows the amplifier and rc filter in front of the adc to be chosen based on the signal bandwidth of interest and not based on the settling requirements of the switched capacitor sar adc inputs. additionally, the ad4001 can be driven with a much higher source impedance than traditional sars, which means the resistor in the rc filter can have a value 10 times larger than previous sar designs and, with high-z mode enabled, can tolerate even larger impedance. figure 41 shows the thd performance for various source impedances with high-z mode disabled and enabled. 15368-228 ?125 ?120 ?115 ?110 ?105 ?100 ?95 ?90 ?85 ? 80 11 02 0 input frequency (khz) 150 ? high-z disabled 150 ? high-z enabled 510 ? high-z disabled 510 ? high-z enabled 1k ? high-z disabled 1k ? high-z enabled figure 41. thd vs. input frequency for various source impedance, v ref = 5 v figure 42 and figure 43 show the ad4001 snr and thd performance using the ada4077-1 (i quiescent = 400 a/amplifier) and ada4610-1 (i quiescent = 1.5 ma/amplifier) precision amplifiers when driving the ad4001 at the full throughput of 2 msps for high-z mode enabled and disabled with various rc filter values. these amplifiers achieve 93 db to 96 db typical snr and better than ?110 db thd with high-z mode enabled. thd is approximately 10 db better with high-z mode enabled, even for large r values. snr holds up close to 96db, even with a very low rc bandwidth cutoff. when high-z mode is enabled, the adc consumes approximately 2 mw/msps extra power; however, this power is still significantly lower than using dedicated adc drivers like the ada4807-1 . for any system, the front end usually limits the overall ac/dc performance of the signal chain. it is evident from the data sheets of the selected precision amplifiers, shown in figure 42 and figure 43, that their own noise and distortion performance dominates the snr and thd specification at a certain input frequency. 260khz 1.3k ? 470pf 498khz 680 ? 470pf 1.3mhz 680? 180pf 2.27mhz 390 ? 180pf 4.42mhz 200 ? 180pf rc filter bandwidths (hz), resistor ( ? ), capacitor (pf) 15368-439 73 76 79 82 85 88 91 94 97 snr (db) ada4077-1 high-z disabled ada4077-1 high-z enabled ada4610-1 high-z disabled ada4610-1 high-z enabled figure 42. snr vs. rc filter bandwidth for various precision adc drivers, v ref = 5 v, f in = 1 khz (turbo mode on, high-z enabled/disabled), vio = 3.3 v
data sheet ad4001 rev. 0 | page 21 of 33 15368-440 rc filter bandwidths (hz), resistor ( ? ), capacitor (pf) 260khz 1.3k ? 470pf 498khz 680 ? 470pf 1.3mhz 680 ? 180pf 2.27mhz 390? 180pf 4.42mhz 200 ? 180pf ?125 ?120 ?115 ?110 ?105 ?100 ?95 ?90 ?85 ? 80 thd (db) ada4077-1 high-z disabled ada4077-1 high-z enabled ada4610-1 high-z disabled ada4610-1 high-z enabled figure 43. thd vs. rc filter bandwidth for various precision adc drivers, v ref = 5 v, f in = 1 khz (turbo mode on, high-z enabled/disabled) long acquisition phase the ad4001 also features a very fast conversion time of 290 ns, which results in a long acquisition phase. the acquisition is further extended by a key feature of the ad4001 ; the adc returns back to the acquisition phase typically 100 ns before the end of the conversion. this feature provides an even longer time for the adc to acquire the new input voltage. a longer acquisition phase reduces the settling requirement on the driving amplifier, and a lower power/bandwidth amplifier can be chosen. the longer acquisition phase means that a lower rc filter cutoff can be used, which means a noisier amplifier can also be tolerated. a larger value of r can be used in the rc filter with a corresponding smaller value of c, reducing amplifier stability concerns without affecting distortion performance significantly. a larger value of r also results in reduced dynamic power dissipation in the amplifier. see table 10 for details on setting the rc filter bandwidth and choosing a suitable amplifier. voltage reference input a 10 f (x7r, 0805 size) ceramic chip capacitor is appropriate for the optimum performance of the reference input. for higher performance and lower drift, use a reference such as the adr4550 . use a low power reference such as the adr3450 at the expense of a slight decrease in the noise performance. it is recommended to use a reference buffer, such as the ada4807-1 , between the reference and the adc reference input. it is important to consider the optimum capacitance size necessary to keep the reference buffer stable as well as to meet the minimum adc requirement previously stated in this section (that is, a 10 f ceramic chip capacitor). power supply the ad4001 uses two power supply pins: a core supply (vdd) and a digital input/output interface supply (vio). vio allows direct interface with any logic between 1.8 v and 5.5 v. to reduce the number of supplies needed, vio and vdd can be tied together for 1.8 v operation. the adp7118 low noise, cmos, low dropout (ldo) linear regulator is recommended to power the vdd and vio pins. the ad4001 is independent of power supply sequencing between vio and vdd. additionally, the ad4001 is insensitive to power supply variations over a wide frequency range, as shown in figure 44. 80 75 70 65 60 55 50 psrr (db) 100 1k 10k 100k 1m frequency (hz) 15368-302 figure 44. psrr vs. frequency, vio = 3.3 v, v ref = 5 v the ad4001 powers down automatically at the end of each conversion phase; therefore, the power scales linearly with the sampling rate. this feature makes the device ideal for low sampling rates (even of a few hertz) and battery-powered applications. figure 45 shows the ad4001 total power dissipation and individual power dissipation for each rail. 100k 100 10k 1 10 1k 0.1 0.01 power dissipation (w) 10 1m 100k 10k 1k 100 throughput (hz) vdd vio v ref total power 15368-220 figure 45. power dissipation vs. throughput, vio = 1.8 v, v ref = 5 v digital interface although the ad4001 has a reduced number of pins, it offers flexibility in its serial interface modes. the ad4001 can also be programmed via 16-bit spi writes to the configuration registers. when in cs mode, the ad4001 is compatible with spi, qspi?, digital hosts, and dsps. in this mode, the ad4001 can use either a 3-wire or 4-wire interface. a 3-wire interface using the cnv, sck, and sdo signals minimizes wiring connections, which is useful, for instance, in isolated applications. a 4-wire interface using the sdi, cnv, sck, and sdo signals allows cnv, which initiates the conversions, to be independent of the readback
ad4001 data sheet rev. 0 | page 22 of 33 timing (sdi). this interface is useful in low ji tter sampling or simultaneous sampling applications. t he ad4001 provides a daisy - chain feature using the sdi input for cascading multiple adcs on a single data line similar to a shift register. th e mode in which the device operates depends on the sdi level when the cnv rising edge occurs. cs mode is selected if sdi is high, and daisy - chain mode is selected if sdi is low. the sdi hold time is such that when sdi and cnv are connected together, daisy - chain mode is always selected. in either 3 - wire or 4 - wire mode , the ad4001 offer s the option of forcing a start bit in front of the data bits. this start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. otherwise, without a busy indicator, the user must time out the maximum convers ion time prior to readback. the busy indicator feature is enabled i n cs mode if cnv or sdi is low when the adc conversion ends. the state of sdo on power - up is either low or h igh - z depending on the states of cnv and sdi , as shown in in table 11. table 11 . state of sdo on power -up cnv sdi sdo 0 0 l ow 0 1 hi gh -z 1 0 low 1 1 high -z the ad4001 has turbo mode capability in both 3 - wire and 4 - wire mode. turbo mode is enabled by writing to the configuration register and replaces the busy indicator feature when enabled. turbo mode allows a slower spi clock rate , making interfacing simpler. a throughput rate of 2 msps can be achieved only with turbo mode enabled and a minimum sck rate of 70 mhz . status bits can also be clocked out at the end of the conversion data if the status bits are enabled in the configuration register. there are six sta tus bits in total , as described in table 12. the ad4001 is configured by 16 - bit spi writes to the desired configuration register. t he 16 - bit word can be written via the sdi line while cnv is held low . the 16 - bit word consists of an 8 - bit header and 8 - bit register data. for isolated systems, the adum141d is recommended, which has a max imum clock rate of 70 mhz and allows the ad4001 to run at 2 msps. register read/write functionality the ad4001 register bits are programmable , and their default status es are shown in table 12 . the register map is shown in table 14. the overvoltage clamp flag is a read only sticky bit , and it is cleared only if the register is read and the overvoltage condition is no longer present. it gives an indication of overvoltage condition when it i s set to 0. table 12 . register bits register bits default status overvoltage ( ov ) c lamp f lag 1 bit (default 1: inactive ) span c ompression 1 bit (default 0: disabled ) high -z m ode 1 bit (default 0: disabled ) turbo m ode 1 bit (default 0: disabled ) enable s ix s tatus b its 1 bit (default 0: disabled ) all access to the register map must start with a write to the 8 - b it command register in the spi interface block. the ad4001 ignores all 1 s until the first 0 is clocked in; the value loaded into th e command regi ster is always a 0 followed by seven command bits. this com mand determines whether that operation is a write or a read. the ad4001 command register is shown in table 13. table 13 . command register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wen r/ w 0 1 0 1 0 0 all register read/writes must occur while cnv is low. data on sdi is clocked in on the rising edge of sck. data on sdo is clocked out on the falling edge of sck. at the end of the data transfer , sdo is put in a high impedance state on the rising edge of cn v if daisy - chain mode is not enabled . if daisy - chain mode is enabled , sdo goes low on the rising edge of cnv. register reads a re not allowed in daisy - chain mode. register write requires three signal lines: sck, cnv, and sdi. during register write, to read the current conversion results on sdo, the cnv pin must be brought low after the conversion is completed ; otherwise, the conversion results may be incorrect on sdo ; however, the register write occur s regardless . the lsb of each configuration register is re served because a user reading 16 - bit conversion data may be limited to a 16 - bit spi frame. the state of sdi on the last bit in the sdi frame may be the state that then persists when cnv rises. because the state of sdi when cnv rises is part of how the user sets the interface mode, the user in this scenario may need to set the final sdi state on that basis. the timing diagram s in figure 46 through figure 48 show how data is read and written when the ad4001 is configured in register read, write , and daisy - chain mode. table 14. register map addr [1:0] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset 0x0 reserved reserved reserved enable six status bits span compression high - z mode turbo mode overv oltage ( ov ) c lamp f lag (read only sticky bit ) 0x e1
data sheet ad4001 rev. 0 | page 23 of 33 t cyc t sck t dis t sckl t sckh t scnvsck t ssdisck t hsdisck t cnvh t en cnv sck 1234567 01 1 0 101 00 b0 b1 b2 b3 b4 b5 b6 wen r/w 0 1 01 addr[1:0] 8 9 10 11 12 13 14 15 16 sdi sdo t hsdo t dsdo b7 x d17 d16 d15 d14 d13 d12 d11 d10 15368-021 figure 46. register read timing diagram (x means dont care) 1 conversion result on d[15:0] d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 t cyc t sck t sckl t sckh t scnvsck t ssdisck t hsdisck t cnvh 1 en cnv 1 the user must wait t conv when reading back the conversion result and performing a register write at the same time. sck 12345 00 1 010100 wen r/w 0 1 0 1 addr[1:0] 9 10 111213141516 sdi sdo b0 b1 b2 b3 b4 b5 b6 b7 t hsdo t dsdo t hcnvsck 15368-022 figure 47. register write timing diagram sdi a sdo a /sdi b sdo b 0 0 command (0x14) 0 0 command (0x14) 0 0 command (0x14) t cyc t sck t sckl t sckh t scnvsck cnv sck 1 24 t dis t cnvh data (0xab) data (0xab) 15368-023 figure 48. register write timing diagram, daisy-chain mode
ad4001 data sheet rev. 0 | page 24 of 33 status word the 6-bit status word can be appended to the end of a conversion result, and the default conditions of these bits are defined in table 15. the status bits must be enabled in the register setting. when the overvoltage clamp flag is a 0, it indicates an overvoltage condition. the overvoltage clamp flag status bit updates on a per conversion basis. the sdo line goes to high-z after the sixth status bit is clocked out (except in daisy-chain mode). the user is not required to clock out all status bits to start the next conversion. the serial interface timing for cs mode, 3-wire without busy indicator, including status bits, is shown in figure 49. table 15. status bits (default conditions) bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 overvoltage (ov ) clamp flag span compression high-z mode turbo mode reserved reserved sdo d15 d14 d13 d1 d0 sck 123 1415 16 t sck t sckl t sckh t hsdo t dsdo cn v conversion a cquisition t cyc acquisition sdi = 1 t cnvh acq t en 21 22 t quiet2 status bits b[5:0] b1 t dis b0 20 t conv 15368-024 figure 49. cs mode, 3-wire without busy indicator serial interface timing diagram, including status bits (sdi high)
data sheet ad4001 rev. 0 | page 25 of 33 cs mode, 3-wire turbo mode this mode is typically used when a single ad4001 is connected to an spi-compatible digital host. it provides additional time during the end of the adc conversion process to clock out the previous conversion result, providing a lower sck rate. the ad4001 can achieve a throughput rate of 2 msps only when turbo mode is enabled and using a minimum sck rate of 70 mhz. the connection diagram is shown in figure 50, and the corresponding timing diagram is shown in figure 51 . this mode replaces the 3-wire with busy indicator mode by programming the turbo mode bit, bit 1 (see table 14). when sdi is forced high, a rising edge on cnv initiates a conversion. the previous conversion data is available to read after the cnv rising edge. the user must wait t quiet1 time after cnv is brought high before bringing cnv low to clock out the previous conversion result. the user must also wait t quiet2 time after the last falling edge of sc k to when cnv is brought high. when the conversion is complete, the ad4001 enters the acquisition phase and powers down. when cnv goes low, the msb is output to sdo. the remaining data bits are clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the 16 th sck falling edge or when cnv goes high (whichever occurs first), sdo returns to high impedance. ad4001 sdi sdo cnv sck convert data in clk digital host v io 15368-125 figure 50. cs mode, 3-wire turbo mode connection diagram (sdi high) sdi = 1 t cyc cnv a quisition aquisition t acq t sck t sckl conversion sck d0 d1 d13 d14 d15 sdo t en t hsdo 123 1 4 1 51 6 t dsdo t dis t sckh t quiet1 quiet2 conv 15368-029 figure 51 . cs mode, 3-wire turbo mode serial interface timing diagram (sdi high)
ad4001 data sheet rev. 0 | page 26 of 33 cs mode, 3-wire without busy indicator this mode is typically used when a single ad4001 is connected to an spi-compatible digital host. the connection diagram is shown in figure 52, and the corresponding timing diagram is shown in figure 53. with sdi tied to vio, a rising edge on cnv initiates a conversion, selects cs mode, and forces sdo to high impedance. after a conversion is initiated, it continues until completion irrespective of the state of cnv. this feature can be useful, for instance, to bring cnv low to select other spi devices, such as analog multiplexers; however, cnv must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the ad4001 enters the acquisition phase and powers down. when cnv goes low, the msb is output onto sdo. the remaining data bits are clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the 16 th sck falling edge or when cnv goes high (whichever occurs first), sdo returns to high impedance. there must not be any digital activity on sck during the conversion. ad4001 sdi sdo cnv sck convert data in clk digital host v io 15368-025 figure 52. cs mode, 3-wire without busy indicator connection diagram (sdi high) sdo d15 d14 d13 d1 d0 t dis sck 123 141516 t sck t sckl t sckh hsdo t dsdo cnv conversion a cquisition t cyc acquisition sdi = 1 t cnvh t acq t en t quiet2 t conv 15368-026 figure 53. cs mode, 3-wire without busy indicator serial interface timing diagram (sdi high)
data sheet ad4001 rev. 0 | page 27 of 33 cs mode, 3-wire with busy indicator this mode is typically used when a single ad4001 is connected to an spi-compatible digital host with an interrupt input ( irq ). the connection diagram is shown in figure 54, and the corresponding timing diagram is shown in figure 55. with sdi tied to vio, a rising edge on cnv initiates a conversion, selects cs mode, and forces sdo to high impedance. sdo is maintained in high impedance until the completion of the conversion irrespective of the state of cnv. prior to the minimum conversion time, cnv can select other spi devices, such as analog multiplexers; however, cnv must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low impedance. with a pull-up resistor on the sdo line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. the ad4001 then enters the acquisition phase and powers down. the data bits are then clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the optional 17 th sck falling edge or when cnv goes high (whichever occurs first), sdo returns to high impedance. if multiple ad4001 devices are selected at the same time, the sdo output pin handles this contention without damage or induced latch-up. meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. there must not be any digital activity on the sck during the conversion. sdi sdo cnv sck convert data in clk digital host vio irq vio 47k ? ad4001 15368-027 figure 54. cs mode, 3-wire with busy indicator connection diagram (sdi high) sdo d15 d14 d1 d0 t dis sck 123 151617 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc acquisition sdi = 1 t cnvh t acq t quiet2 15368-028 figure 55. cs mode, 3-wire with busy indicator serial interface timing diagram (sdi high)
ad4001 data sheet rev. 0 | page 28 of 33 cs mode, 4-wire turbo mode this mode is typically used when a single ad4001 is connected to an spi-compatible digital host. it provides additional time during the end of the adc conversion process to clock out the previous conversion result, giving a lower sck rate. the ad4001 can achieve a throughput rate of 2 msps only when turbo mode is enabled and using a minimum sck rate of 70 mhz. the connection diagram is shown in figure 56, and the corresponding timing diagram is shown in figure 57. this mode replaces the 4-wire with busy indicator mode by programming the turbo mode bit, bit 1 (see table 14). the previous conversion data is available to read after the cnv rising edge. the user must wait t quiet1 time after cnv is brought high before bringing sdi low to clock out the previous conversion result. the user must also wait t quiet2 time after the last falling edge of sck to when cnv is brought high. when the conversion is complete, the ad4001 enters the acquisition phase and powers down. the adc result can be read by bringing its sdi input low, which consequently outputs the msb onto sdo. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the 16 th sck falling edge or when sdi goes high (whichever occurs first), sdo returns to high impedance. ad4001 sdi sdo cnv sck convert data in clk digital host irq vio 47k ? cs1 15368-032 figure 56. cs mode, 4-wire turbo mode connection diagram acquisition sdo sck acquisition sdi cnv t ssdicnv t hsdicnv t cyc t sck t sck l t en t hsdo 123 1 4 1 51 6 t dsdo t dis t sckh d15 d14 d13 d1 d0 t quiet1 t quiet2 t acq conversion t conv 15368-034 figure 57. cs mode, 4-wire turbo mode timing diagram
data sheet ad4001 rev. 0 | page 29 of 33 cs mode, 4-wire without busy indicator this mode is typically used when multiple ad4001 devices are connected to an spi-compatible digital host. a connection diagram example using two ad4001 devices is shown in figure 58, and the corresponding timing is shown in figure 59. with sdi high, a rising edge on cnv initiates a conversion, selects cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback. if sdi and cnv are low, sdo is driven low. prior to the minimum conversion time, sdi can select other spi devices, such as analog multiplexers; however, sdi must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the ad4001 enters the acquisition phase and powers down. each adc result can be read by bringing its sdi input low, which consequently outputs the msb onto sdo. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the 16 th sck falling edge or when sdi goes high (whichever occurs first), sdo returns to high impedance and another ad4001 can be read. ad4001 sdi sdo cnv sck ad4001 sdi sdo cnv sck device b device a convert data in clk digital host cs1 cs2 15368-030 figure 58 . cs mode, 4-wire without busy indicator connection diagram sdo d15 d14 d13 d1 d0 t dis sck 12 3 30 31 32 t hsdo t dsdo t en conversion a cquisition t conv cyc t acq acquisition sdi(cs1) cnv t ssdicnv t hsdicnv d1 14 15 t sck t sckl t sckh d0 d15 d14 17 18 16 sdi(cs2) t quiet2 15368-031 figure 59 . cs mode, 4-wire without busy indicator serial interface timing diagram
ad4001 data sheet rev. 0 | page 30 of 33 cs mode, 4-wire with busy indicator this mode is typically used when a single ad4001 is connected to an spi-compatible digital host with an interrupt input, and when it is desired to keep cnv, which samples the analog input, independent of the signal used to select the data reading. this independence is particularly important in applications where low jitter on cnv is desired. the connection diagram is shown in figure 60, and the corresponding timing is shown in figure 61. with sdi high, a rising edge on cnv initiates a conversion, selects cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback. if sdi and cnv are low, sdo is driven low. prior to the minimum conversion time, sdi can select other spi devices, such as analog multiplexers; however, sdi must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low impedance. with a pull-up resistor on the sdo line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. the ad4001 then enters the acquisition phase and powers down. the data bits are then clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the optional 17 th sck falling edge or when sdi goes high (whichever occurs first), sdo returns to high impedance. ad4001 sdi sdo cnv sck convert data in clk digital host irq vio 47k ? cs1 15368-032 figure 60 . cs mode, 4-wire with busy indicator connection diagram sdo d15 d14 d1 d0 t dis sck 123 151617 t sck t sckl t sckh t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition sdi cnv t ssdicnv t hsdicnv t quiet2 15368-033 figure 61. cs mode, 4-wire with busy indicator serial interface timing diagram
data sheet ad4001 rev. 0 | page 31 of 33 daisy-chain mode use this mode to daisy-chain multiple ad4001 devices on a 3-wire or 4-wire serial interface. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using two ad4001 devices is shown in figure 62, and the corresponding timing is shown in figure 63. when sdi and cnv are low, sdo is driven low. with sck low, a rising edge on cnv initiates a conversion, selects daisy-chain mode, and disables the busy indicator. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when the conversion is complete, the msb is output onto sdo, and the ad4001 enters the acquisition phase and powers down. the remaining data bits stored in the internal shift register are clocked out of sdo by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck rising edges. each adc in the daisy-chain outputs its data msb first, and 16 n clocks are required to read back the n adcs. the data is valid on both sck edges. the maximum conversion rate is reduced because of the total readback time. it is possible to write to each adc register in daisy-chain mode. the timing diagram is shown in figure 48. this mode requires 4-wire operation because data is clocked in on the sdi line with cnv held low. the same command byte and register data can be shifted through the entire chain to program all adcs in the chain with the same register contents, which requires 8 (n + 1) clocks for n adcs. it is possible to write different register contents to each adc in the chain by writing to the furthest adc in the chain, first using 8 (n + 1) clocks, and then the second furthest adc with 8 n clocks, and so forth until reaching the nearest adc in the chain, which requires 16 clocks for the command and register data. it is not possible to read register contents in daisy-chain mode; however, the 6 status bits can be enabled if the user wants to know the adc configuration. note that enabling the status bits requires 6 extra clocks to clock out the adc result and the status bits per adc in the chain. turbo mode cannot be used in daisy-chain mode. convert data in clk digital host device b device a ad4001 sdi sdo cnv sck ad4001 sdi sdo cnv sck 15368-036 figure 62. daisy-chain mode connection diagram sdo a = sdi b d a 15 d b 15 d b 14 d b 13 d a 14 d a 13 d a 1d a 0 d a 1d a 0 d b 1d b 0 sck 1 2 3 303132 t ssdisck t hsdisck conversion acquisition t conv t cyc t acq acquisition cnv 14 15 t sck t sckl t sckh 17 18 16 sdi a = 0 sdo b d a 15 d a 14 t hsdo t dsdo t quiet2 t hsckcnv t dis t quiet2 t en 15368-037 figure 63. daisy-chain mode serial interface timing diagram
ad4001 data sheet rev. 0 | page 32 of 33 layout guidelines the pcb that houses the ad4001 must be designed so that the analog and digital sections are separated and confined to certain areas of the board. the pinout of the ad4001 , with its analog signals on the left side and its digital signals on the right side, eases this task. avoid running digital lines under the device because they couple noise onto the die, unless a ground plane under the ad4001 is used as a shield. fast switching signals, such as cnv or clocks, must not run near analog signal paths. avoid crossover of digital and analog signals. at least one ground plane must be used. it can be common or split between the digital and analog sections. in the latter case, join the planes underneath the ad4001 devices. the ad4001 voltage reference input (ref) has a dynamic input impedance. decouple the ref pin with minimal parasitic inductances by placing the reference decoupling ceramic capacitor close to (ideally right up against) the ref and gnd pins and connect them with wide, low impedance traces. finally, decouple the vdd and vio power supplies of the ad4001 with ceramic capacitors, typically 100 nf, placed close to the ad4001 and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. an example of a layout following these rules is shown in figure 64 and figure 65. 15368-038 figure 64 . example layout of the ad4001 (top layer) 15368-039 figure 65 . example layout of the ad4001 (bottom layer) evaluating the ad4001 performance other recommended layouts for the ad4001 are outlined in the documentation of the evaluation board for the ad4001 ( eval-ad4001fmcz ). the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the eval- sdp-ch1z .
data sheet ad4001 rev. 0 | page 33 of 33 outline dimensions compliant to jedec standards mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 10 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 coplanarity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 66. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters 2.48 2.38 2.23 0.50 0.40 0.30 10 1 6 5 0.30 0.25 0.20 pin 1 index area seating plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed pad 3.10 3.00 sq 2.90 p i n 1 i n d i c a t o r ( r 0 . 1 5 ) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 0 2-05-2013- c top view bottom view 0.20 min figure 67. 10-lead lead frame chip scale package [lfcsp] 3 mm 3 mm body and 0.75 mm package height (cp-10-9) dimensions shown in millimeters ordering guide model 1 integral nonlinearity (inl) temperature range package description ordering quantity package option branding ad4001brmz 0.4 lsb ?40c to +125c 10-lead msop tube, 50 rm-10 c8h ad4001brmz-rl7 0.4 lsb ?40c to +125c 10-lead msop reel, 1000 rm-10 c8h AD4001BCPZ-RL7 0.4 lsb ?40c to +125c 10-lead lfcsp reel, 1500 cp-10-9 c8h eval-ad4001fmcz ad4001 evaluation board compatible with eval-sdp-ch1z 1 z = rohs compliant part. ?2017 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d15368-0-1/17(0)

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